code review 104770047: armasm: add VFP, golden testdata

armasm/decode.go

 // Copyright 2014 The Go Authors.  All rights reserved.
 // Use of this source code is governed by a BSD-style
 // license that can be found in the LICENSE file.
 
 package armasm
 
 import (
         "encoding/binary"
         "fmt"
 )
@@ skipping 111 matching lines @@
 // _pm_ means ± (usually keyed by the U bit).
 // The _W suffix indicates a general addressing mode based on the P and W bits.
 // The _offset and _postindex suffixes force the given addressing mode.
 // The rest should be somewhat self-explanatory, at least given
 // the decodeArg function.
 type instArg uint8
 
 const (
         _ instArg = iota
         arg_APSR
+        arg_FPSCR
+        arg_Dn_half
         arg_R1_0
         arg_R1_12
         arg_R2_0
         arg_R2_12
         arg_R_0
         arg_R_12
+        arg_R_12_nzcv
         arg_R_16
         arg_R_16_WB
         arg_R_8
         arg_R_rotate
         arg_R_shift_R
         arg_R_shift_imm
         arg_SP
+        arg_Sd
+        arg_Sd_Dd
+        arg_Dd_Sd
+        arg_Sm
+        arg_Sm_Dm
+        arg_Sn
+        arg_Sn_Dn
         arg_const
         arg_endian
+        arg_fbits
+        arg_fp_0
         arg_imm24
         arg_imm5
         arg_imm5_32
         arg_imm5_nz
         arg_imm_12at8_4at0
         arg_imm_4at16_12at0
+        arg_imm_vfp
         arg_label24
         arg_label24H
         arg_label_m_12
         arg_label_p_12
         arg_label_pm_12
         arg_label_pm_4_4
         arg_lsb_width
         arg_mem_R
         arg_mem_R_pm_R_W
         arg_mem_R_pm_R_postindex
         arg_mem_R_pm_R_shift_imm_W
         arg_mem_R_pm_R_shift_imm_offset
         arg_mem_R_pm_R_shift_imm_postindex
         arg_mem_R_pm_imm12_W
         arg_mem_R_pm_imm12_offset
         arg_mem_R_pm_imm12_postindex
         arg_mem_R_pm_imm8_W
         arg_mem_R_pm_imm8_postindex
+        arg_mem_R_pm_imm8at0_offset
         arg_option
         arg_registers
         arg_registers1
         arg_registers2
         arg_satimm4
         arg_satimm5
         arg_satimm4m1
         arg_satimm5m1
         arg_widthm1
 )
 
 // decodeArg decodes the arg described by aop from the instruction bits x.
 // It returns nil if x cannot be decoded according to aop.
 func decodeArg(aop instArg, x uint32) Arg {
         switch aop {
         default:
                 return nil
 
         case arg_APSR:
                 return APSR
+        case arg_FPSCR:
+                return FPSCR
 
         case arg_R_0:
                 return Reg(x & (1<<4 - 1))
         case arg_R_8:
                 return Reg((x >> 8) & (1<<4 - 1))
         case arg_R_12:
                 return Reg((x >> 12) & (1<<4 - 1))
         case arg_R_16:
                 return Reg((x >> 16) & (1<<4 - 1))
 
+        case arg_R_12_nzcv:
+                r := Reg((x >> 12) & (1<<4 - 1))
+                if r == R15 {
+                        return APSR_nzcv
+                }
+                return r
+
         case arg_R_16_WB:
                 mode := AddrLDM
                 if (x>>21)&1 != 0 {
                         mode = AddrLDM_WB
                 }
                 return Mem{Base: Reg((x >> 16) & (1<<4 - 1)), Mode: mode}
 
         case arg_R_rotate:
                 Rm := Reg(x & (1<<4 - 1))
                 typ, count := decodeShift(x)
@@ skipping 22 matching lines @@
         case arg_R1_12:
                 return Reg(((x >> 12) & (1<<4 - 1)))
         case arg_R2_0:
                 return Reg((x & (1<<4 - 1)) | 1)
         case arg_R2_12:
                 return Reg(((x >> 12) & (1<<4 - 1)) | 1)
 
         case arg_SP:
                 return SP
 
+        case arg_Sd_Dd:
+                v := (x >> 12) & (1<<4 - 1)
+                vx := (x >> 22) & 1
+                sz := (x >> 8) & 1
+                if sz != 0 {
+                        return D0 + Reg(vx<<4+v)
+                } else {
+                        return S0 + Reg(v<<1+vx)
+                }
+
+        case arg_Dd_Sd:
+                return decodeArg(arg_Sd_Dd, x^(1<<8))
+
+        case arg_Sd:
+                v := (x >> 12) & (1<<4 - 1)
+                vx := (x >> 22) & 1
+                return S0 + Reg(v<<1+vx)
+
+        case arg_Sm_Dm:
+                v := (x >> 0) & (1<<4 - 1)
+                vx := (x >> 5) & 1
+                sz := (x >> 8) & 1
+                if sz != 0 {
+                        return D0 + Reg(vx<<4+v)
+                } else {
+                        return S0 + Reg(v<<1+vx)
+                }
+
+        case arg_Sm:
+                v := (x >> 0) & (1<<4 - 1)
+                vx := (x >> 5) & 1
+                return S0 + Reg(v<<1+vx)
+
+        case arg_Dn_half:
+                v := (x >> 16) & (1<<4 - 1)
+                vx := (x >> 7) & 1
+                return RegX{D0 + Reg(vx<<4+v), int((x >> 21) & 1)}
+
+        case arg_Sn_Dn:
+                v := (x >> 16) & (1<<4 - 1)
+                vx := (x >> 7) & 1
+                sz := (x >> 8) & 1
+                if sz != 0 {
+                        return D0 + Reg(vx<<4+v)
+                } else {
+                        return S0 + Reg(v<<1+vx)
+                }
+
+        case arg_Sn:
+                v := (x >> 16) & (1<<4 - 1)
+                vx := (x >> 7) & 1
+                return S0 + Reg(v<<1+vx)
+
         case arg_const:
                 v := x & (1<<8 - 1)
                 rot := (x >> 8) & (1<<4 - 1) * 2
                 if rot > 0 && v&3 == 0 {
                         // could rotate less
                         return ImmAlt{uint8(v), uint8(rot)}
                 }
                 if rot >= 24 && ((v<<(32-rot))&0xFF)>>(32-rot) == v {
                         // could wrap around to rot==0.
                         return ImmAlt{uint8(v), uint8(rot)}
                 }
                 return Imm(v>>rot | v<<(32-rot))
 
         case arg_endian:
                 return Endian((x >> 9) & 1)
 
+        case arg_fbits:
+                return Imm((16 << ((x >> 7) & 1)) - ((x&(1<<4-1))<<1 | (x>>5)&1))
+
+        case arg_fp_0:
+                return Imm(0)
+
         case arg_imm24:
                 return Imm(x & (1<<24 - 1))
 
         case arg_imm5:
                 return Imm((x >> 7) & (1<<5 - 1))
 
         case arg_imm5_32:
                 x = (x >> 7) & (1<<5 - 1)
                 if x == 0 {
                         x = 32
                 }
                 return Imm(x)
 
         case arg_imm5_nz:
                 x = (x >> 7) & (1<<5 - 1)
                 if x == 0 {
                         return nil
                 }
                 return Imm(x)
 
         case arg_imm_4at16_12at0:
                 return Imm((x>>16)&(1<<4-1)<<12 | x&(1<<12-1))
 
         case arg_imm_12at8_4at0:
                 return Imm((x>>8)&(1<<12-1)<<4 | x&(1<<4-1))
+
+        case arg_imm_vfp:
+                x = (x>>16)&(1<<4-1)<<4 | x&(1<<4-1)
+                return Imm(x)
 
         case arg_label24:
                 imm := (x & (1<<24 - 1)) << 2
                 return PCRel(int32(imm<<6) >> 6)
 
         case arg_label24H:
                 h := (x >> 24) & 1
                 imm := (x&(1<<24-1))<<2 | h<<1
                 return PCRel(int32(imm<<6) >> 6)
 
@@ skipping 110 matching lines @@
                         return nil
                 }
                 sign := int8(+1)
                 if u == 0 {
                         sign = -1
                 }
                 imm := int16((x>>8)&(1<<4-1)<<4 | x&(1<<4-1))
                 mode := AddrMode(uint8(p<<1) | uint8(w^1))
                 return Mem{Base: Rn, Mode: mode, Offset: int16(sign) * imm}
 
+        case arg_mem_R_pm_imm8at0_offset:
+                Rn := Reg((x >> 16) & (1<<4 - 1))
+                u := (x >> 23) & 1
+                sign := int8(+1)
+                if u == 0 {
+                        sign = -1
+                }
+                imm := int16(x&(1<<8-1)) << 2
+                return Mem{Base: Rn, Mode: AddrOffset, Offset: int16(sign) * imm}
+
         case arg_option:
                 return Imm(x & (1<<4 - 1))
 
         case arg_registers:
                 return RegList(x & (1<<16 - 1))
 
         case arg_registers2:
                 x &= 1<<16 - 1
                 n := 0
                 for i := 0; i < 16; i++ {
@@ skipping 38 matching lines @@
                         count = 32
                 }
         case RotateRight:
                 if count == 0 {
                         typ = RotateRightExt
                         count = 1
                 }
         }
         return typ, uint8(count)
 }